Many electronic devices are fabricated in wafer form. For example, integrated circuits, sensor, light emitting diodes, and low temperature co-fired ceramic (LTCC) devices are fabricated in wafer form. Following fabrication, functional devices are typically singulated and then separately packaged.
Singulated semiconductor dice, oftentimes called chips, require individual packaging in order to both firmly attach the dice and provide for electrical and thermal interconnection. The format is generally referred to as a first level of packaging that is required to convert from very small interconnections to larger ones that are capable of being in turn connected to a system for power and signal distribution to the die. Such first-level packages may also be useful for testing functionality of the die prior to further connecting to a system.
The packaging steps include at least provision for a permanent substrate, often called a header; interconnection, typically by wire bonding or flip-chip method; and encapsulation by overmolding or lid attachment. The header often contains further provision for electrical and thermal connection to a circuit board. It is commonly recognized that steps involving handling of individual devices in chip form are much more expensive than steps that are completed in wafer form. This is due to the relative difficulty and time consuming steps involved in separately handling singulated chips. A method is sought that enables encapsulation of devices in wafer form, prior to singulation, while simultaneously providing for flexible interconnection to other chips or boards.
The trend is towards a so-called “chip scale package”, where the dimensions of the package surrounding the semiconductor dice are comparable to those of the dice itself. For example, the lateral dimensions of the package may be no more than 1.2 times that of the dice. The drivers for chip-scale packaging are both to reduce overall system cost and volume.
Most typically, a chip scale package includes a substrate to which the dice is bonded, and allowance for wire-bonding connections between the dice and the substrate. In a common variation termed as flip-chip, the semiconductor dice termination pads are prepared for simultaneous mechanical and electrical interconnection to a substrate. The dice is inverted onto a substrate having matching pads and the electrical and mechanical connections are accomplished. For example, the interconnection medium may be solder or electrically-conductive epoxy. Ideally, such flip-chip interconnection may allow for solder balls arranged in a dense array, termed a ball grid array (BGA). Such arrays may allow for hundreds or thousands of electrical and thermal interconnections to be simultaneously.
In the pursuit of reduced cost and size of electronics systems, a clear direction for development is 3D. Chip stacking is becoming an increasingly important way to reduce volumes. It is highly desirable to extend interconnection of semiconductor dice vertically without limit. That is, one dice is attached above a second, and so on to form a 3-D stack. Many workers have proposed various methods for accomplishing such stacking. However, no generalized method allowing for unlimited number of dice to be stacked to form a complete system has been proposed.
However, new challenges arise with 3D chip stacking, including requirements for chip-to-chip interconnect. A particular problem that must be addressed with vertically stacked semiconductor dice is that of heat dissipation. As overall system volumes are dramatically reduced by stacking various subsystems in close proximity, the heat dissipation requirements escalate. In fact, normal conductive or air convection methods of heat dissipation may be limiting. To be widely useful, an infinitely stackable device and method must include provision for heat dissipation by conduction to a liquid. This leads to the conclusion that such an interconnection device and method must allow for fluidic connections, as well as electrical connections.
As semiconductor dice clock speeds are steadily increased, limitations on signal propagation are being approached. Electrical signal propagation is limited by parasitic resistances and capacitances, with associated “RC delay times”. While there are challenges to be overcome in converting back-and-forth from electrical to optical domain, there are clear advantages for signal propagation. Therefore, a generalized solution for stackable dice should include capability for optical signal propagation. Additionally, the maximum distance that a signal must propagate within a subsystem is proportional to the diagonal of the dice itself. It is desirable to reduce this distance. If the same subsystem normally constructed on a single dice in a 2-D plane were divided into much smaller components and stacked to form an interconnected 3-D system, the maximum distance that a signal must propagate within the subsystem is then proportional to the diagonal of the cube so formed. Another opportunity is to combine multiple subsystems into a fully interconnected system, thereby providing further improvements in signal propagation delay.
A new solution must enable easily partitioning of functionality such that integrated circuits or Micro-Electro-Mechanical Systems (MEMS) devices prepared on silicon, glass, ceramic or semiconductor substrates can be interconnected and packaged with minimal interference or interaction between the device wafer fabrication and the packaging approach. Such partitioning will ideally allow for the initial packaging enclosure to be placed over a device in the same clean room where the devices are manufactured. In this manner, such initial packaging can be completed almost immediately following preparation of the devices in their most sensitive state (i.e. MEMS release, or deposition of sensitive materials). No good solution to these problems has been developed to date.
Both performance and reliability of the subject devices depends intimately on the ability to flexibly customize all packaging materials to be compatible with the enclosed devices. For example, accelerometers, gyros and pressure sensors require that coupling of parasitic stresses from the package be minimized, which in turn requires that all materials have close match in coefficient of thermal expansion and low creep. Depending on the materials used in construction of the device, this requirement might in turn create a demand that packaging materials be constructed of ceramic, glass, silicon, silicon carbide or III-V semiconductor. In addition, the need for good thermal management may lead to a requirement for high thermal conductivity materials; or high frequency devices may require ultra-low loss dielectrics. Clearly, a packaging approach that enables a variety of materials to be flexibly interchanged is highly desirable.
Many miniature devices requiring packaging involve sensitive components, such as moveable elements, or materials that may degrade by exposure to ordinary atmospheric conditions. For example, MEMS devices involve the integration of elements such as accelerometers, gyros, RF switches on a common silicon substrate. Microelectronics fabrication procedures result in such device being released as a final process step. Ideally, these devices should be immediately protected from dust or from chemical contamination in order to ensure long-term viability. In other applications, biological materials may be placed in a prepared cavity on a wafer, and these materials should be sealed to prevent oxidation or chemical contamination. In both cases, it is desirable to seal the device in a cavity with a controlled ambient ranging from vacuum to controllably reactive gases to inert gases. In each case, the packaged devices may become components of a comprehensive systems-on-a-chip (SOAC) strategy. With the constant demand for reduced cost and size of systems, along with higher reliability, such SOAC approaches are gaining increasing interest.
The miniaturization of mechanical systems promises new directions in science and technology. The major markets for MEMS are in optical communications, biotechnology, automotive industry, and radio frequency (RF) applications. MEMS sensors and actuators are commonplace in automobiles to replace existing devices with improved performance, reduced cost, and better reliability. The rapid increase of MEMS applications requires a more thorough study of MEMS packaging. One of the challenges that MEMS packaging faces is that the environments in which MEMS devices operate can vary dramatically with each application.
Applications of MEMS-based devices encompass a vast spectrum of sciences and technologies. Common MEMS applications comprise sensors for temperature, pressure, flow rate, humidity, and chemical and medical applications; uses in fluidics such as pumps dispensers, flow-meters, and valves; inertial devices such as accelerometers, position sensors, and gyroscopes; actuators of all types including rotators, steppers, drivers, and positioners; optical devices such as mirrors, lenses, gratings, filters, choppers, detectors, switches, and wave guides; and thermal management devices such as heaters, cooling devices, and heat pipes. Furthermore, these individual devices can be integrated into one package or system to perform a myriad of operations in a compact package. Nevertheless, MEMS can be broken down into several classifications by industry: automotive, military/aerospace, biological, optical, and telecommunications.
MEMS are not limited to purely mechanical and electrical systems, but also have many uses when tapping into the area of optics. This branch of MEMS is known as micro-electro-optical-mechanical systems (MOEMS). MOEMS consist mostly of optical switches for communications. MOEMS make possible high speed switching without the conversion of optical signals to electrical and back to optical. The backbones of the Internet are primarily optical systems that consist of fiber-optic cables that connect continents, major cities, and large technical centers.
In the field of high frequency communications, radio frequency (RF) MEMS has enabled increasingly smaller and more portable communications products. RF MEMS switches can be used as phase shifters for use in beam steering in electronically steerable radar arrays. Another application is the use in tunable filters and tunable matching networks. A considerable size reduction can be gained by replacing a switched filter bank with a discretely tunable filter, in which switches may be embedded into the filter network directly. This changes the lumped element reactances or transmission line resonators that create the filter response. Furthermore, multifunctional capability—i.e. to transmit and receive in different bands or to have concurrent communications and radar functions—is increasing in demand for microwave systems. RF MEMS devices can be used as the control component in such systems.
However, current implementations of MEMS and MOEMS devices, such as RF MEMS switches, or SOAC approaches are limited by lack of cost-effective and reliable packaging methods to accommodate the enclosed devices and to merge with current world-wide fabrication capabilities. In recent years, costs of packaging and testing have dramatically increased from the norm of perhaps 10-20 percent of total cost, to 60-70 percent of total cost. Responses to this steady shift in costs from integrated circuit to packaging and testing have been slow to arrive. At the same time, demand is increasing to accommodate different domains, such as optical, microwave, or microfluidics simultaneously with electrical.
Nagarajan et al, in U.S. Pat. No. 6,846,725, disclose a specific method for packaging sensitive electronic devices. This method fails to meet the broad-based challenges inherent in device-level packaging in several respects. First, the method requires that the “device wafer” receive custom processing following end of normal fabrication procedures. In this method, two wafers are metallized and joined as an initial step. Subsequent steps relate to forming a through-substrate via and filling the via. This method is in stark contrast to the desired partitioning, where a device wafer is completed normally and immediately attached to a capping die or wafer. Second, the approach inherently assumes that vias will be formed through the entire normal thickness, typically 500-650 microns, of the capping die or wafer. Such approach is undesirable since the expense of forming through-substrate vias is roughly proportional to the depth of the via, but also because the lateral area consumed by such via increases in direct proportion to the thickness of the via. For example, assuming that a via fabricated in a substrate has a slope angle of 85 degrees, a via through a 500 micron thick substrate will etch laterally by about 44 microns. This means that, for a via that must be at least 2 microns in diameter, a space of (2*44+2)=90 microns is required. This method has the effect of dramatically restricting Input-Output (I/O) interconnect density. While this problem could in principle be solved by simply increasing the 85 degree angle to 90 degrees, such slope is extremely difficult to metallize uniformly, leading to difficulties in filling the vias with conductive metal. In addition, during fabrication some tolerance of the design angle must be anticipated in order to prevent population distributions including actual reentrant angles which are virtually impossible to cover with metal. Third, the defined approach does not anticipate optical, fluidic or thermal vias. Fourth, the approach does not define the capability to continue 3D stacking of die. Fifth, whereas conductive materials filling vias will often have a coefficient of thermal expansion (CTE) that is substantially higher than that of silicon, it is important to minimize the volume of material in the via in order to reduce stresses associated with this CTE mismatch. From this perspective, smaller vias are inherently more reliable. From these various problems, it is apparent that the method disclosed by Nagarajan et al is very limited in scope and that there is a need for a more universal solution accommodating a range of materials and functional domains.
The lifecycle of the development of a MEMS-based solution begins with the definition of the function to be required of the device. The device must be designed, modeled, and optimized while taking into consideration the materials used and the environmental conditions under which the device will operate. Before the device is fabricated, a packaging and interconnection scheme must be developed to provide for protection and for electrical connections to the system. The packaged device is tested, optimizations are made, and the design, modeling, fabrication, and packaging steps are repeated and refined until an acceptable product is ready for use. Testing may occur before the device has been packaged; but since the package almost always affects performance, it is necessary to perform tests after encapsulation to verify that the original specifications and requirements have not been compromised beyond acceptable levels. Finally, a manufacturing process must be developed for mass production. Due to the interdependency of each step upon the other, the entire system design must be considered at the inception of the design process rather than focusing on each aspect individually.
Choosing materials that are readily available and easily processed makes the task of high volume production easier, but these materials may not provide the performance needed for the device. Conversely, exotic or rarely used materials that provide excellent performance may prove problematic in bringing the device to market due to high cost of manufacturing, difficulties in processing, or poor throughput or yield. Therefore, finding new uses for existing materials with known and mature processing techniques is one of the most promising venues for increasing the development of new applications and market penetration of MEMS devices.
Whereas wirebonding interconnection has most frequently been the interconnect technology of choice, this technology is not extensible to 3D interconnections. So called flip-chip or solder bump interconnects is the leading favorite in these emerging applications, since many interconnections can be prepared in advance and formed simultaneously. In addition, solder reflow has the advantage of self-alignment due to “wicking action” of the solder. For a multiple-chip stack assembly, such self-alignment is extremely important to overcome misalignment tolerancing issues. Finally, wirebonding typically applies thermocompression with addition of ultrasonic scrubbing. Both temperature, compression and ultrasonic energy may be incompatible with the enclosed devices.
Through substrate vias (TSV) are a necessary element of 3D chip stacking techniques. As such, TSV is a primary enabling technology for 3D approaches. Whereas with some substrate materials, such as wire-in-glass, the TSV is readily provided, with typical substrate materials used in the microelectronics industry, the procedure will involve etching a patterned hole through the wafers, perhaps providing electrical insulation in the via, filling the vias with highly conductive material, and providing for attachment by solder bump or other method. For high I/O multiple wafer (die) interconnection, it will also be very important to provide for routing of the electrical connection through the entire stack. In addition, due to heat dissipation, it may be very important to allow for thermal management simultaneously with electrical connection. Finally, it is highly desirable to include provisions for optical and microfluidic TSV.
In many devices that operate at high frequencies, such as greater than 1 gigahertz, parasitic capacitance and inductance limit performance, while dielectric losses lead to reduction of transmitted signals. Devices which are interconnected primarily by wire bonds suffer from parasitics associated with the wire itself. For this reason, flip chip methods of die attachment are often preferred for high frequency devices. Conventional methods of incorporating the flip chip approach typically involve attachment of a device chip to a board. Such attachment accomplishes both electrical, mechanical and thermal attachment. Advantageously, interconnection lengths are short, resulting in reduced parasitic capacitance, inductance and resistance. However, thermal dissipation paths are constrained to be along solder bumps that are designed to provide optimum electrical and mechanical connections, with little consideration for thermal dissipation. In flexible vertically integrated systems, electrical, mechanical and thermal connections must all be optimized. Therefore, there is a need to extend the application of flip chip methods to accommodate all design variations.
For MEMS devices to be applied at high frequency, such as the RF MEMS switch, it is required to minimize parasitic capacitance and inductance but also to select materials with reliably low dielectric loss.
While a number of wafer-to-wafer bonding techniques have been made available, these techniques generally involve application of high temperature to achieve hermeticity. In addition, maintaining a hermetic environment over a long period of time requires that all materials have very low outgassing rates, and may require the inclusion of active getters. A need exists for an encapsulation method that maintains low cost, interconnection flexibility, and additionally allows for hermeticity and the incorporation of active getters.
It is common to be concerned about the yield of devices, since cost is directly impacted by yield. It is well known that by coupling a number of devices of unknown “goodness” into a system, the expectation is that the combined yield will suffer and costs will escalate. A successful fabrication strategy must be appropriately partitioned such that “known good die” (KGD) are assembled using highly reliable assembly procedures that do not result in further yield loss mechanisms. Typically, devices fabricated on a wafer are tested for functionally and at least some performance parameter prior to singulation. Once packaging steps are completed, devices are normally tested again to identify and sort out defects that have been introduced during the packaging steps themselves. Any new approaches to encapsulation and interconnection of devices must anticipate the requirements for testing of devices. For example, high frequency devices cannot be fully tested while in wafer form since the interconnections themselves become part of the circuitry. MEMS devices requiring high mechanical Q may not exhibit typical operating parameters unless they are enclosed in vacuum. Discrete devices may share a common substrate and cannot be accurately tested in wafer form since they are electrically connected. New methods must carefully consider and accommodate the needs for KGD and for device testing at the lowest point of assembly.
U.S. Pat. No. 6,846,725, issued 25 Jan. 2005, filed 27 Jan. 2003 (foreign application priority date 17 Oct. 2002), “Wafer-Level Packaging for MEMS”, discloses a method for wafer-level packaging which includes forming electrical through-vias.
U.S. Pat. No. 6,638,784, issued 28 Oct. 2003, filed 24 Jun. 1999, protects “Hermetic Chip Scale Packaging Means and Method Including Self Test”.
Analog Devices U.S. Pat. No. 6,534,340, issued 18 Mar. 2003, filed 18 Nov. 1998 protects “Cover Cap for semiconductor wafer devices”. This patent envisions a wafer that is photoetchable or transparent to be attached as a cover to a substrate including a number of semiconductor devices.
U.S. Pat. No. 6,828,674, filed 5 Jun. 2002 and U.S. Pat. No. 6,441,481, filed 5 Jun. 2002, address “Hermetically Sealed Microstructure packages”. A capping wafer is included. However, electrical connection is by wirebond following bonding of the two wafers, preferably with fritted glass, and wirebond is further encapsulated by an overmold.
U.S. Pat. No. 6,465,281, issued 15 Oct. 2002, filed 8 Sep. 2000, “Method of Manufacturing a Semiconductor Wafer Level Package”, discloses a capping wafer bonded to a semiconductor wafer with fritted glass. No provision is made for electrical or optical through-vias.
U.S. Pat. No. 6,806,557, issued 19 Oct. 2004, filed 30 Sep. 2002, “Hermetically Sealed Microdevices having a Single Crystalline Silicon Getter for maintaining Vacuum”, discloses a silicon capping wafer having a cavity and a roughened surface that performs as a getter.
U.S. Pat. No. 6,656,768, filed 8 Feb. 2001 and U.S. Pat. No. 6,507,082, filed 8 Feb. 2001, “Flip-Chip Assembly of Protected Micromechanical devices”, protects low-cost ceramic packages, including BGA, by coating the IC surface with a protective material, selectively etching the coating for solder ball attachment, and singulating and flip-chip assembling.
U.S. Pat. No. 6,452,238, issued 17 Sep. 2002, filed 27 Sep. 2000, “MEMS Wafer Level Package”, includes wafer level encapsulation, enclosing a device within a hermetic cavity formed by etching the capping wafer prior to attach.
US 2002/0090749, filed about January 2001, “Hermetic Package for MEMS Devices with Integrated Carrier”, includes a capping wafer which may have features such as ports which allow MEMS devices to interact with the environment.
US 2002/0089044, filed about January 2001, “Hermetic MEMS Package with Interlocking Layers”, complements the above patent filing.
US 2002/0113296, filed 31 Oct. 2001, “Wafer Level Hermetic Sealing Method”, relates to a device that is hermetically sealed at wafer level. A capping wafer is attached using adhesives such as low melting point solder.
US 2003/0160310, filed 26 Feb. 2002, protects “Micro-machined Semiconductor Package”. Discussed is a hermetic multi-layered ceramic semiconductor package.
US 2003/0160021, filed 27 Feb. 2002, “Bonding for a MEMS and MEMS based devices”, discloses a method of packaging MEMS devices which includes a Solid-Liquid interdiffusion process, comprised of layers of Chromium, Gold and Indium and resulting in a hermetic seal.
U.S. Pat. No. 5,193,738, issued 16 Mar. 1993, “Methods and apparatus for soldering without flux”, includes inkjet solder application in inert ambient.
U.S. Pat. No. 6,114,187, issued 5 Sep. 2000, “Method for preparing a chip scale package and product produced by the method”, discloses application of inkjet printing to apply solder as well as dielectric materials.
US 2004/0088855, filed 11 Nov. 2002, “Interposers for Chip-Scale Packages, Chip-Scale Packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and Methods”. Describes interposer along with bumping and lateral redistribution. Limited to electrical interconnection and does not anticipate 3D stacking.
Reference is also made to the following documents: U.S. Pat. No. 7,019,408, 28 Mar. 2006, Bolken et al.; U.S. Pat. No. 6,235,554, 22 May 2001, Akram et al.; U.S. Pat. No. 6,107,109, August 2000, Akram et al.; U.S. Pat. No. 6,097,087, August, 2000, Farnworth et al.; U.S. Pat. No. 6,020,629, February 2000, Farnworth et al.; T R. Anthony, “Forming electrical interconnections through semiconductor wafers”, J. Appl. Phys., Vol. 52, No. 8, Aug. 1981, pp. 5340-5349; and “Chip Scale Review”, Vol. 1, No. 1, May 1997.
From the problems discussed above, it is apparent that there is a need to provide an alternative to the encapsulation and interconnection of many devices that are fabricated in wafer form. A multi-functional capping chip solves various problems in encapsulation and interconnection of devices while simultaneously making provision for further vertical integration.
In view of the foregoing, the present invention is directed towards an improved device and method to enable stacking of semiconductor dice while simultaneously forming electrical, thermal, fluidic and optical interconnections.
With the exception of customization of termination metal on the semiconductor dice, a device must be constructed that allows for minimal changes in the semiconductor dice fabrication. Semiconductor dice fabrication is complex and expensive. To enable rapid implementation of chip-scale packages, the package must accommodate a variety of dice. The present invention is also directed to a device and method enabling improved packaging and interconnection of multiple semiconductor dice.